1. Field of the Invention
The present invention relates to a coincidence circuit for judging the coincidence between binary data and, particularly, to a circuit for judging the coincidence between n-bits of binary data and an n-bit counter output.
2. Description of the Related Art
Such a coincidence circuit is applied, for example, to control a current conduction time for heating resistors in accordance with image data such as gradation data or the like, in a thermal recording apparatus. The coincidence circuit has a basic arrangement, for example, as shown in FIG. 7.
In FIG. 7, the reference numeral 10 represents an n-bit counter having n-stages of D-type flip-flops 11(1), 11(2), . . . , 11(n), each having a Q output fed back to its own D input. The flip-flops 11(1), 11(2), . . . , 11(n) are connected in series with one another by connecting the Q output of the flip-flop of one stage to the clock terminal (CK) of the flip-flop of the next stage. In the counter 10, the Q output of the flip-flop 11(1) corresponds to the least significant bit, the respective Q outputs of the subsequent flip-flops 11(2), . . . , 11(n-1) correspond to subsequent bits, and the Q output of the flip-flop 11(n) corresponds to the most significant bit. The clock terminal (CK) of the flip-flop 11(1), which corresponds to the least significant bit, is the input terminal of the counter 10 to which a count signal is applied.
The reference numeral 20 represents a latch circuit for storing n-bit binary data. The latch circuit 20 has n stages of D-type flip-flops 21(1), 21(2), . . . , 21(n). A latch signal is applied to clock terminals (CK) of the respective flip-flops 21(1), 21(2), . . . , 21(n) so that, upon application of the latch signal, the most significant bit D1 is held by the flip-flop 21(1), the subsequent bits D2, . . . , Dn-1 are held by the subsequent flip-flops 21(2), . . . , 21(n-1), and the most significant bit Dn is held by the flip-flop 21(n). The latch signal applied to the latch circuit 20 is also applied through an inverter 12 to clear terminals (CL) of the respective flip-flops 11(1), 11(2), . . . , 11(n) of the counter 10 so that the counter 10 is cleared simultaneously with the holding of the n-bit data in the latch circuit 20.
The Q outputs of the respective flip-flops 21(i) (i=1,2, . . . ,n), which are the respective output bits of the latch circuit 20, and the corresponding output bits of the counter 10, i.e., the Q outputs of the respective flip-flops 11(i) (i=1,2, . . . ,n), are applied to respective exclusive NOR (hereinafter referred to as "ENOR") gates 14(i) (i=1,2, . . . ,n). The outputs of the respective ENOR gates 14(1), 14(2), . . . ,14(n) corresponding to the respective output bits of the counter 10 and the respective output bits of the latch circuit 20 are applied to an AND gate 16. The output of AND gate 16 is applied to the clock terminal of a D-type flip-flop 18. The Q output of the flip-flop 18 is fed back to its own D input so that its Q output is inverted whenever a clock is applied to its clock terminal (CK).
In the coincidence circuit, when the count value of the counter 10 becomes coincident with the latched data in the latch circuit 20, the respective outputs of all the ENOR gates 14(1), 14(2), . . . , 14(n) are high and the output of the AND gate 16 becomes high so as to apply a clock to the flip-flop 18. The Q output of the flip-flop 18 is, thus, turned on as a coincidence judgment output.
In the above-mentioned coincidence circuit, in the case where the data to be held by the latch circuit 20 are gradation data representing one dot in a thermal recording operation, the current conduction control for the respective heating resistors corresponding to radation data can be realized if a current is made to flow into one of the heating resistors corresponding to the dot during a period beginning with a count start of the counter 10 until a coincidence judgment output.
However, such a coincidence circuit using ENOR gates for detecting the coincidence between n-bit binary data and corresponding bits of a counter, and further using a judgment circuit (the AND gate 16 and the flip-flop 18 in FIG. 7) for judging the detection of the coincidence in all the ENOR circuits, occupies a comparatively large area of a semiconductor integrated circuit (IC). This is because, in the above-mentioned coincidence circuit, the coincidence between the two bits applied to each ENOR gate is detected. Thus, a function must be provided for detecting both when the two bits have a value of "1" and when they have a value of "0", thereby making the circuit arrangement comparatively complicated.
Specifically, in the case of a MOS integrated circuit, MOS transistors are used as basic elements, and each basic element is formed into a NAND gate, a NOR gate or an inverter. More complex gates are realized as composites of these basic gates. The above-mentioned ENOR circuit consists of a NOR gate 22 and two NAND gates 23 and 24, as shown in FIG. 8. The NOR gate and the NAND gate each comprises four MOS transistors as shown in FIG. 9(a) and FIG. 9(b), respectively, and, therefore, twelve MOS transistors are necessary to constitute an ENOR gate. Generally, in the case of a functional circuit such as an ENOR gate that is formed as a composite gate constituted by a plurality of basic gates, the more complicated the function to be realized, the larger the scale of the circuit.